1. Field of the Invention
The present invention relates to a current mirror circuit in an analog IC such as an LCD driver IC, which forms a large number of current sources placed in a wide area of an IC chip.
2. Description of the Related Art
In an analog IC, when many constant current sources are required, a current mirror circuit which forms a large number of constant current sources with using one constant current source as a reference is often used. FIG. 6A shows a conventional current mirror circuit which is usually used, and FIG. 6B is a characteristic diagram of the current mirror circuit of FIG. 6A.
Referring to FIG. 6A, a constant reference potential Vref is applied to the gate of a P-channel MOS field-effect transistor (hereinafter, xe2x80x9cPMOSxe2x80x9d) Q0 to form a constant current source I61. A constant current Iref outputted from the constant current source I61 is supplied to an N-channel MOS field-effect transistor (hereinafter, xe2x80x9cNMOSxe2x80x9d) Qref6 in which the drain and the gate are connected to each other and the source is connected to the ground GND. The NMOS Qref6 is used as an input transistor (i.e., a mirror source transistor) of the current mirror circuit, and NMOSs Q61 to Q6n are used as output transistors (i.e., mirror destination transistors). The sources of the output transistors Q61 to Q6n are connected to the source of the input transistor Qref6 through a feeder line Ws6. The gates of the output transistors Q61 to Q6n are connected to the gate of the input transistor Qref6 through a potential line Wp6. According to the configuration, the gate potentials of the output transistors Q61 to Q6n are equal to the gate potential of the input transistor Qref6. The figure xe2x80x9cVddxe2x80x9d denotes the power source potential.
Even when a conductor wire such as an aluminum wire is used as the feeder line Ws6, the feeder line has wiring resistance Rw to some extent. In the case where a large number of output transistors Q61 to Q6n are distributed in a wide range, the voltage drop due to the wiring resistance Rw and a current cannot be negligible. This state is shown in FIG. 6B.
Referring to FIG. 6, no current flows through the potential line Wp6, and hence the gate potentials of the output transistors Q61 to Q6n are equal to the gate potential of the input transistor Qref6. On the other hand, because of the voltage drop in the feeder line Ws6, the source potentials of the output transistors Q61 to Q6n are sequentially raised as moving along the placement positions of the output transistors Q61 to Q6n. As compared with the gate-source voltage Vgs of the input transistor Qref6, therefore, the gate-source voltages Vgs of the output transistors Q61 to Q6n are sequentially smaller as moving along the placement positions. As a result, depending on the placement position, each of the output transistors Q61 to Q6n is enabled to supply only a current of a level which is considerably different from a desired current level.
FIG. 7 shows a configuration in which feeder lines are arrange in a star-like shape in order to avoid the influence of the voltage drop caused by a feeder line. A constant current Iref output from a current source I71 is supplied to an NMOS Qref7 in which the drain and the gate are connected to each other. The NMOS Qref7 is used as an input transistor of a current mirror circuit, and NMOSs Q71 to Q7n are used as output transistors. The sources of the input transistor Qref7 and the output transistors Q71 to Q7n are connected to a common point K through feeder lines Ws7r and Ws71 to Ws7n, respectively, and then connected to the ground GND. According to the configuration, the gate-source voltages Vgs of the output transistors Q71 to Q7n are equal to the gate-source voltage Vgs of the input transistor Qref7.
FIG. 8 shows a configuration in which an interface based on a gate voltage is not produced and a current interface is realized in order to avoid the influence of the voltage drop caused by a feeder line (see the following document xe2x80x9cDesign of Analog CMOS Integrated Circuitsxe2x80x9d). In a current mirror circuit having the current interface configuration of FIG. 8, a plurality xe2x80x9cnxe2x80x9d of or PMOSs Q01 to Q0n are disposed in a current source I81, and a reference voltage Vref is commonly applied to the gates so that a constant current Iref is flown through each of the PMOSs Q01 to Q0n. The constant currents Iref are supplied to NMOSs Qref81 to Qref8n in each of which the drain and the gate are connected to each other, and which are input transistors, through feeder lines Ws81 to Ws8n, respectively. NMOSs Q81 to Q8n which are output transistors are connected to the input transistors Qref81 to Qref8n so as to constitute respective current mirror configurations. According to the configuration, regardless of the difference among lengths of the feeder lines Ws81 to Ws8n, i.e., different resistances, the same gate-source voltage Vgs is supplied to all the output transistors Q81 to Q8n. Therefore, a current of a desired level can be supplied.
Behzad Razavi, xe2x80x9cDesign of Analog CMOS Integrated Circuitsxe2x80x9d McGraw-Hill, 2001, Sec. 18.2 Analog Layout Techniques, p.p. 642-643 is known as a related document.
In the conventional current mirror circuit of the star arrangement shown in FIG. 7, the feeder lines must be individually prepared and set so as to have the same length which is equal to the length of the longest feeder line, in order to equalize the resistances of all the feeder lines Ws7r and Ws71 to Ws7n. In the current mirror circuit of the current interface configuration shown in FIG. 8, the feeder lines Ws81 to Ws8n whose number are equal to the number of the current mirror output transistors must be individually disposed, and the current mirror configurations each of which is configured by input and output transistors must be produced. In the current mirror circuits of the conventional configurations of FIGS. 7 and 8, when a large number of output transistors are disposed, therefore, a large wiring area is required for forming the feeder lines. In the case where hundreds of output transistors are used, such as in an LCD driver IC, a very large wiring area is required, and hence the chip size of the IC is increased.
An object of the invention is to provide a current mirror circuit which has a large number (such as hundreds) of output transistors, in which an influence due to the wiring resistance of a feeder line can be remarkably reduced without increasing the wiring area for forming the feeder line.
The invention provides a current mirror circuit, which has a plurality of output transistors serving as current mirror outputs, including: a first input transistor whose one end is connected to a first constant current source and whose another end is connected to a first connecting position at a first potential, which is used as an input side of a current mirror; a second input transistor whose one end is connected to a second constant current source, which is disposed with being separated from said first input transistor by a predetermined distance and is used as an input side of a current mirror; a first feeder line which connects said other end of said first input transistor with another end of said second input transistor; a first potential line which connects said one end of said first input transistor with said one end of said second input transistor with a resistance that is higher than a resistance of said first feeder line, to produce a potential gradient; and a plurality of output transistors distributed between said first input transistor and said second input transistor, which are coupled to said first feeder line and said first potential line and are used as an output side of a current mirror.
Moreover, the current mirror circuit further includes: a third input transistor whose one end is connected to a third constant current source, which is disposed with being separated from said second input transistor by a predetermined distance in an opposite direction to said first input transistor and is used as an input of a current mirror; a second feeder line which connects said other end of said second input transistor with another end of said third input transistor; a second potential line which connects said one end of said second input transistor with said one end of said third input transistor with a resistance that is higher than a resistance of said second feeder line, to produce a potential gradient; and a plurality of output transistors distributed between said second input transistor and said third input transistor, which are coupled to said second feeder line and said second potential line and is used as an output side of a current mirror.
Furthermore, said another end of said third input transistor is connected to a second connecting position at the first potential.
Furthermore, said first potential line is polysilicon line and said second first potential line is polysilicon line.
Furthermore, said first and second input transistors and said output transistors are P-channel MOS transistors and said third input transistor is also P-channel MOS transistor.
Furthermore, said first and second input transistors and said output transistors are N-channel MOS transistors and said third input transistor is also N-channel MOS transistor.